The present invention relates generally to the field of real-time data scaling, and is specifically concerned with a high-speed scaler that requires relatively little hardware.
An important application of real-time data scaling is the conversion of coded digital data, representing the magnitude of a quantity or measurement, into a display decimal format which can be understood by a human operator. Such scaling operations are essential to the effective operation of radar, targeting, or fire control systems which generate coded digital signals representing the distance to a target. Because it is desirable to display an up-to-date indication of distance to the target, the coded digital signals must be scaled; that is, the numbers are converted from an unscaled digital code representing the distance to a different digital code that represents the distance in meters or feet or other units which are readily comprehensible to human operators. This information is then displayed for the operator of the distance-measuring equipment.
The time required to complete the scaling places a limit on the frequency of updates to the distance display. When an accurate real time display of distance is required, updates must be almost continuous, and the scaling circuitry must be capable of high data throughput rates. To process scaled data quickly, systems in the past have employed either a software- or a hardware-intensive architecture.
In the software-intensive approach, data is scaled by executing a multiply/accumulate/divide algorithm. The time required to execute the algorithm varies directly with the number of data bits scaled. For example, the steps required for one software-intensive scaling system operating on N bits of data are as follows:
______________________________________ CLOCK INSTRUCTION CYCLES ______________________________________ Load Scale Value 1 Load input value 1 Signed Multiply algorithm N Load Scale Value (divide) 1 Signed division algorithm N+5 Binary-BCD conversion 2N+3 Total clock cycles: 4N+11 ______________________________________
When N is large, such systems can only be made to operate at high speeds if the host processor operates at a high clock speed. As data input rates increase, this system becomes undesirable even with a high speed processor, because the processor resources must be dedicated almost entirely to the scaling operation. At very high data rates, these systems are impractical since even a high-speed processor will not provide adequate throughput.
In the hardware-intensive approach, a memory device is used for scale processing. The memory is loaded with binary scaled output values, and the input value is used to address the memory, selecting the data in the memory that is the scaled equivalent of the input. Then, binary-to-BCD conversion hardware operates on the data output from the memory to produce signals suitable for driving a display. The processing speed of such a system is the sum of access time of the memory devices used and the time required for a hardware Binary-BCD conversion. Typical conversion times are:
______________________________________ N Access Time (nS) ______________________________________ 8 72 16 252 24 459 32 612 ______________________________________
This approach is extremely fast, but has several disadvantages. The hardware-intensive approach requires large amounts of memory. For exact scaling of a 16-bit word, for example, a 64K memory block is required for each scale factor used. This requirement also entails a large number of integrated circuit chips. The chip count problem is exacerbated because the Binary-BCD conversion hardware gets very large as the number of output bits increases. For example, two chips are required for N=8, eight chips for N=16, and thirty-three chips for N=32.
Neither of these approaches is entirely satisfactory. When high display update frequency is desired, the high data rates involved make software-intensive scaling impractical. Yet the alternative, a hardware-intensive scaling system, requires many integrated circuit chips which are expensive and which also add size and weight to the display system. Thus, there is a need for a scaling system that operates at high speeds, yet does not require a large chip count.